Recent input-output (I/O) interface circuits for integrated circuits use differential input buffers in which the input signal is compared to a reference voltage Vref, which is equal to one-half of the positive power supply voltage Vddq applied to the I/O interface circuits.
In some applications, such as DRAM integrated circuits, on-die termination (ODT) is used to improve input signal fidelity by providing an on-chip impedance (referred to as the “termination impedance”) between the input signal and the positive power supply voltage Vddq as well as the input signal and the reference power supply voltage Vss (usually the ground voltage). Furthermore, in some applications, such as DRAM integrated circuits, off-chip driver impedance adjustment (OCD) is provided to enable the output drive strength of the integrated circuit to be set to a target value using an off-chip resistor as a reference impedance. The on-die termination impedance and the output drive strength (or output drive impedance) are provided as on-chip impedance where the on-chip impedance is typically set using an impedance matching scheme to match the on-chip impedance to an off-chip resistor at a given reference voltage Vref. The reference voltage is typically equal to one-half of the power supply voltage Vddq.
In some implementations, an on-chip calibration circuit is used to calibrate an on-chip reference impedance which is then used to set the on-chip impedance for ODT or OCD. Conventional calibration circuits typically implement an impedance matching scheme to set the on-chip reference impedance to match the impedance of the off-chip resistor. A reference voltage Vref of one-half of the positive power supply voltage Vddq is supplied to the integrated circuit and the calibration circuit calibrates the on-chip reference impedance to match the impedance of the off-chip resistor at the reference voltage Vref. Once calibrated, the on-chip reference impedance of the calibration circuit is then used to set the termination impedance for on-die termination or the output driver impedance for output drive strength.
FIG. 1 illustrates a calibration scheme using impedance matching for setting an on-chip impedance of an integrated circuit to match an off-chip resistor in some examples. Referring to FIG. 1, the conventional calibration scheme involves connecting a current source or a pull-up circuit 2 between a positive power supply voltage Vddq and an off-chip resistor RZQ. In the present description, power supply voltages Vddq and Vssq refer to the positive power supply voltage and the reference power supply voltage, respectively, used for the input-output (I/O) circuits of the integrated circuit. The reference power supply voltage Vssq can be the ground voltage. On the other hand, the positive power supply voltage Vdd refers to the positive power supply voltage used for the internal circuits of the integrated circuit. The positive power supply voltage Vddq and the positive power supply voltage Vdd may have the same voltage value or may have different voltage values.
The current of the current source or the strength of the pull-up circuit 2 is adjusted by changing logic states to increase the number of active pullup elements or by changing bias voltages to the pull-up circuit until the voltage at a common node ZQ between the pull-up circuit 2 and the off-chip resistor RZQ is equal to the reference voltage Vref provided to the integrated circuit. The reference voltage is typically one-half of the power supply voltage Vddq, i.e. Vref=½Vddq. In that case, the impedance of the pull-up circuit 2 would be equal to the impedance of the off-chip resistor RZQ. This is true because the voltages across the off-chip resistor RZQ and the pull-up circuit 2 are equal (i.e. ½*Vddq) and the current through the elements are also equal since they are connected in series. Based on Ohm's Law (resistance R=V/I), the resistances (or impedances) of the pull-up circuit 2 and the off-chip resistor RZQ would therefore be equal.
To set the impedance of the pull-down circuit, the final logic states or bias conditions for the pull-up circuit 2 are applied to a mirror pull-up circuit 3 that is connected in series with a pull-down circuit 4. The mirror pull-up circuit 3, with its impedance set equal to resistor RZQ based on the applied bias conditions, can then be used to calibrate the pull-down circuit 4 using the same impedance matching principle. That is, the impedance of the pull-own circuit 4 is adjusted until the voltage at the common node 5 equals to the reference voltage Vref being one-half of the supply voltage Vddq. Then, the impedance of the pull-down circuit 4 matches the impedance of the mirror pull-up circuit 3 and both are set to equal to the impedance of the off-chip resistor RZQ. With the pull-up and pull-down circuits thus calibrated, their logic states or bias conditions are stored and can then be used to set the actual on-chip impedance used for ODT or OCD to target values.
More specifically, the on-chip impedance is typically implemented using a pull-up circuit, a pull-down circuit, or a pull-up circuit connected in series with a pull-down circuit. The pull-up circuit is typically implemented as one or more PMOS transistors connected in parallel between the positive power supply voltage Vddq and an input/output (I/O) node. In some cases, one or more resistors are placed between the PMOS transistors and the I/O node. The pull-down circuit is typically implemented as one or more NMOS transistors connected in parallel between an output node and the reference power supply voltage Vssq (or ground). In some cases, one or more resistors are placed between the NMOS transistors and the I/O node. As used herein, a “pull-up circuit 1X” refers to a pull-up circuit including one or more parallel connected PMOS transistors that has its impedance set to equal to the impedance of the off-chip resistor RZQ. A pull-up circuit 1X is sometimes referred to as a pull-up circuit unit. Similarly, as used herein, a “pull-down circuit 1X” refers to a pull-down circuit including one or more parallel connected NMOS transistors that has its impedance set to equal to the impedance of the off-chip resistor RZQ. A pull-down circuit 1X is sometimes referred to as a pull-down circuit unit.
In some examples, the calibration circuit calibrates a pull-up circuit unit and a pull-down circuit unit to match the impedance of the off-chip resistor. For instance, during the calibration process, one or more transistors within the pull-up circuit unit are turned on to set the impedance of the pull-up circuit unit to match the impedance of the off-chip resistor RZQ. In one example, a digital code is applied to the bank of PMOS transistors in the pull-up circuit unit to selectively turn on one or more of the PMOS transistors in the pull-up circuit unit to obtain the desired impedance value RZQ. Similarly, during the calibration process, one or more transistors within the pull-down circuit unit are turned on to set the impedance of the pull-down circuit unit to match the impedance of the off-chip resistor RZQ. In one example, a digital code is applied to the bank of NMOS transistors in the pull-down circuit unit to selectively turn on one or more of the NMOS transistors in the pull-down circuit unit to obtain the desired impedance value RZQ. The digital code resulting from the calibration process for the pull-up circuit unit may not be the same as the digital code for the pull-down circuit.
The pull-up circuit unit and the pull-down circuit unit in the calibration circuit are dummy circuits, that is, they are not the actual pull-up/pull-down circuits used to provide the termination impedance used for ODT or the driver impedance for OCD. Instead, the logic states or bias conditions for the dummy pull-up circuit and the dummy pull-down circuit in the calibration circuit are stored and the logic states or bias conditions are applied to the actual pull-up circuit and the actual pull-down circuit to generate the desired on-chip impedance values for on-die termination or output drive strength adjustment. For example, the logic states or bias conditions may be the digital codes used to selectively turn on one or more of the transistors in the pull-up circuit and the pull-down circuit.
FIG. 2 illustrates the results of the conventional calibration scheme. As a result of the impedance matching calibration method, a pull-up circuit unit 6 (Pull Up 1X) is calibrated to have an impedance equal to the impedance of resistor RZQ when the pull-up circuit unit 6 is biased to the reference voltage Vref of ½ Vddq. Furthermore, as a result of the impedance matching calibration method, a pull-down circuit unit 8 (Pull Down 1X) is calibrated to have an impedance equal to the impedance of resistor RZQ when the pull-down circuit unit 8 is biased to the reference voltage Vref of ½*Vddq. The bias conditions for the pull-up circuit unit and pull-down circuit unit obtained from the calibration circuit are applied to the actual pull-up and pull-down circuits to set the impedance of the actual pull-up and pull-down circuits to target values related to the impedance of the off-chip resistor.
In some examples, to set the target impedance value for the on-chip termination or the output driver impedance, the stored digital code for the pull-up circuit is applied to the bank of pull-up transistors to selectively turn on one or more of the pull-up transistors to obtain the target impedance value. Moreover, the stored digital code for the pull-down circuit is applied to the bank of pull-down transistors to selectively turn on one or more of the pull-down transistors to obtain the target impedance value.
FIG. 3 is a circuit diagram of a conventional calibration circuit for setting an on-chip impedance of an integrated circuit to match an off-chip resistor in some examples. Referring to FIG. 3, a calibration circuit 20 implements a current mirror method to calibrate the pull-up impedance and the pull-down impedance to match the impedance of the off-chip resistor at the reference voltage. In the calibration circuit 20 of FIG. 3, PMOS transistor MP1 and PMOS transistor MP2 form a current mirror. The off-chip resistor RZQ is connected in series with transistor MP1 between a power supply voltage Vdd or Vddq and ground. The common node ZQ between the transistor MP1 and resistor RZQ is coupled to a comparator 21 which also receives a reference voltage Vref equal to ½*Vddq. The comparator 21 adjusts the gate bias voltage of the transistor MP1 until the voltage at node ZQ equals the reference voltage Vref. At that point, the impedance of PMOS transistor MP1 is set equal to the resistance of resistor RZQ. Note that in some cases, the power supply voltage Vdd for internal circuitry is used to supply the current mirror transistors MP1 and MP2. In other cases, the power supply voltage Vddq for the I/O circuits is used. The comparator 21 sets the voltage at node ZQ to a value of ½*Vddq which is equal to the reference voltage Vref.
The current flowing in PMOS transistor MP1 (I=Vref/RZQ) is mirrored to PMOS transistor MP2 which is connected in series with a pull-down circuit unit 22. The current through transistor MP2 is the same as the current through transistor MP1 because they are the same size and the terminal voltages are the same. A comparator 24 operates to set the logic states or the bias conditions of the pull-down circuit unit 22 so that the voltage at the common node 23 equals the reference voltage Vref of ½*Vddq. At that point, the impedance of pull-down circuit unit 22 is set equal to the impedance of transistor MP2 which is equal to the resistance of resistor RZQ.
The logic states or bias conditions for the pull-down circuit unit 22 are applied to a mirror pull-down circuit unit 26 which is connected in series with a pull-up circuit unit 28. A comparator 29 operates to set the logic states or bias conditions of the pull-up circuit unit 28 so that the voltage at the common node 27 equals the reference voltage Vref of ½*Vddq. At that point, the impedance of the pull-up circuit unit 28 is set equal to the impedance of the pull-down circuit unit 26 which is equal to the resistance of resistor RZQ.
Through the calibration circuit 20, the logic states or bias conditions to set a pull-up circuit unit and a pull-down circuit unit to match the impedance of the off-chip resistor RZQ are obtained. The logic states or bias conditions are stored by the integrated circuit to be applied to the actual pull-up circuit and the actual pull-down circuit used for ODT or OCD to obtain the desired impedance values. While the calibration circuit 20 of FIG. 3 is able to handle a large capacitance value at the ZQ node, the calibration circuit is more susceptible to instability as the current mirrors and comparators can cause oscillation.
FIG. 4 is a circuit diagram of a conventional calibration circuit for setting an on-chip impedance of an integrated circuit to match an off-chip resistor in some examples. Referring to FIG. 4, a calibration circuit 30 is implemented without the use of current mirrors and therefore the calibration circuit is less susceptible to oscillation. However, the capacitance at the ZQ node receiving the off-chip resistor cannot be too large. In the calibration circuit 30 of FIG. 4, a pull-up circuit unit 32 is connected in series with the off-chip resistor RZQ between the power supply voltage Vddq and ground. The common node ZQ between the pull-up circuit unit 32 and resistor RZQ is coupled to a comparator 34 which also receives a reference voltage Vref equal to ½*Vddq. The comparator 34 varies the logic states or bias conditions of the pull-up circuit unit 32 until the voltage at node ZQ equals the reference voltage Vref. At that point, the impedance of pull-up circuit unit 32 is set equal to the resistance of resistor RZQ.
The logic states or bias conditions for the pull-up circuit unit 32 are applied to a mirror pull-up circuit unit 36 which is connected in series with a pull-down circuit unit 39 between the power supply voltage Vddq and ground. A comparator 38 operates to set the logic states or bias conditions of the pull-down circuit unit 39 so that the voltage at the common node 37 equals the reference voltage Vref of ½*Vddq. At that point, the impedance of pull-down circuit unit 39 is set equal to the resistance of resistor RZQ.
Through the calibration circuit 30, the logic states or bias conditions to set a pull-up circuit unit and a pull-down circuit unit to match the resistance of the off-chip resistor RZQ are obtained. The logic states or bias conditions are stored by the integrated circuit to be applied to the pull-up circuit and the pull-down circuit used for ODT or OCD to obtain the desired impedance values. While the calibration circuit 30 of FIG. 4 achieves greater stability through eliminating the use of current mirrors, the capacitance at the ZQ node has to be no more than a certain value to ensure that calibration can be completed within the desired time.
In conventional integrated circuits, the impedance used for ODT and OCD is specified at a reference voltage Vref of ½*Vddq. Accordingly, the conventional impedance matching calibration scheme described above works well to set the desired on-chip impedance values. However, the conventional impedance matching calibration scheme does not work in applications where a reference voltage Vref other than ½*Vddq is used. For example, in the above-described example, the on-chip termination is realized using equal pull-up and pull-down impedances. Thus, a reference voltage Vref of ½*Vddq can be used as the voltage across the equal pull-up and pull-down impedance. However, in some applications, an integrated circuit may employ high-side termination where the on-chip termination impedance is provided only to the positive power supply Vddq. In that case, the integrated circuit uses a reference voltage Vref that is set to a value higher than half of the power supply Vddq. For example, the integrated circuit may receive a reference voltage that is 0.7*Vddq.
When the reference voltage Vref is not ½*Vddq, the conventional impedance matching calibration scheme does not work because the voltage across the off-chip resistor and the voltage across the pull-up/pull-down circuit to be matched are necessarily different. Pull-up and pull-down circuits are typically constructed using transistors, which are nonlinear devices. Therefore, the impedance must be set at the specified reference voltage Vref value and the impedance cannot be accurately extrapolated from an impedance value calibrated for a reference voltage Vref=½*Vddq. For these reasons, the conventional impedance matching calibration scheme cannot be effectively used to set the on-chip impedance in applications where the reference voltage Vref is not equal to ½*Vddq. A large error may result where the on-chip impedance does not match well with the desired off-chip resistor.